Senior Staff Verification Engineer (f/m/div)

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As a Senior Staff Verification Engineer on our Research & Development team, you\'ll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. What if your ideas could change the way the world connects, powers up, or thinks? Are you in?

Your Role Key responsibilities in your new role You will drive the development and optimization of IP verification environments, ensuring robust and efficient test bench architecture.

Take full ownership of complex IP verification , developing System Verilog - UVM test bench environments Create functional coverage models and write constrained random tests for thorough validation Ensure test benches meet sign-off targets , including coverage and functional safety requirements Debug failing test cases and collaborate in Design and Concept meetings to resolve issues Drive verification strategy and enhance IP test bench architecture for future projects Your Profile Qualifications and skills to help you succeed We are looking for a skilled verification engineer with a collaborative attitude and eagerness to apply and expand industry-standard methodologies.

Bachelor’s degree in Electrical/Electronic Engineering or a related field 8+ years of experience in Verification Engineering , with hands-on exposure to System Verilog - UVM (academic, internship, or professional experience) Strong under