Senior Principal Digital IC Design Engineer

Our client is a globally recognised semiconductor innovator at the forefront of intelligent power and sensing technologies. Their solutions enable advances in automotive, industrial automation, renewable energy, cloud infrastructure, and AI-driven applications. With a strong focus on innovation, sustainability, and engineering excellence, they develop cutting‑edge semiconductor technologies that power the world's most demanding electronic systems. They are seeking an experienced Senior Principal Digital IC Design Engineer to play a key role in the architecture and development of advanced digital IP and embedded systems for next‑generation semiconductor products. Key Responsibilities Lead the architecture, specification, implementation, and optimisation of complex digital IP blocks and embedded systems.

Design and develop digital control peripherals, MCU/DSP subsystems, and hardware accelerator IPs. Evaluate and benchmark new architectures to ensure optimal performance, efficiency, and scalability. Drive improvements in design methodologies, development processes, and engineering quality standards. Provide technical leadership across projects while mentoring and supporting junior engineers. Collaborate closely with cross‑functional product and integration teams to define system requirements and deliver robust semiconductor solutions. Ensure designs meet quality, reliability, timing, and power objectives throughout the development lifecycle. Produce high‑quality technical documentation to support design and product development activities. Qualifications Master's or PhD in Electrical Engineering, Electronics Engineering, or a related discipline.

15+ years of experience in digital IC design within the semiconductor industry. Proven expertise designing digital IP, MCU/DSP architectures, or hardware accelerator solutions. Strong RTL design experience using Verilog and/or SystemVerilog. Experience leading technical projects or engineering teams. Strong understanding of design quality processes, including DFMEA and controlled design release methodologies. Knowledge of timing constraints (SDC), power intent (UPF), and digital design best practices. Excellent technical documentation and communication skills in English. Eligibility to work in Switzerland. Complete RTL‑to‑GDSII design flow, including synthesis, place route, static timing analysis, and power optimisation. Digital signal processing architecture and implementation. Advanced verification methodologies such as UVM. French language skills would be advantageous.

Apply now or send your CV in confidence to Suitable applicants will be contacted with further details regarding the company and opportunity.