Darum lohnt es sich
ppb**All applicants must have the right to work in Switzerland** /b /ppOur client, a cutting-edge semiconductor company working on next-generation compute architectures, is looking for a Senior Physical Design Engineer to take ownership across complex IP and SoC designs.
This is a key technical role focused on high-quality implementation, collaboration, and delivering robust silicon on advanced process nodes. /ppAs a Senior Physical Design Engineer, you’ll be responsible for driving Static Timing Analysis, timing ECOs, power-grid planning, IR-drop analysis, and correlation across synthesis, place-and-route, and sign-off. /ph3Required experience: /h3ulliStrong expertise in either timing closure or power/IR-drop sign-off. /liliProven experience in 2+ successful tapeouts /liliSolid understanding of STA, multi-clock designs, and hierarchical timing closure. /liliProven hands-on experience with synthesis and PR flows on advanced nodes. /liliExperience in power-grid design, IR-drop analysis /liliProficiency in scripting (Tcl, Python) for flow automation and report generation. /li /ul /p #J-18808-Ljbffr
