Senior Hardware Compute Architect (f/m/d)

Senior Hardware Compute Architect

Responsibilities

• Define the hardware architecture of a hybrid compute engine, including execution units (scalar, vector, tensor/matrix), memory hierarchy, memory tiering strategies, and the interfaces required to enable cooperation between electronic and photonic compute domains.

• Architect the system data fabric and interconnect infrastructure, including bandwidth, latency, coherency, and die‑to‑die communication requirements using technologies such as UCIe-class links, CXL, UALink, and NVLink-class fabrics.

• Partner with the Software Compute Architect to define hardware/software interfaces and workload mapping strategies, determining when operations should execute through electronic versus photonic compute paths.

• Evaluate architectural options through quantitative modeling, analyzing performance, power, area, and scalability trade‑offs to guide system‑level decisions before silicon implementation.

• Collaborate with photonics architecture, circuit design, RTL, physical design, and packaging teams to translate compute primitives into implementable system‑level architectures.

• Own the hardware architecture specification through sign‑off, ensuring alignment between system requirements and downstream implementation teams.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.

• 5+ years of experience designing compute hardware architecture at the SoC or system level, ideally involving heterogeneous computing, accelerators, or specialized compute architectures.

• Deep expertise in compute architecture, including execution units (scalar, vector, tensor/matrix), workload mapping, memory hierarchy, and system‑level architecture trade‑offs.

• Strong experience architecting high‑performance interconnects, data fabrics, and heterogeneous compute systems, including technologies such as UCIe, CXL, UALink, NVLink‑class, or comparable architectures.

• Experience with architectural modeling and quantitative analysis of performance, power, area, and system scalability to guide hardware architecture decisions.

• Proven ability to collaborate across hardware and software teams to define interfaces, requirements, and system‑level design decisions.

• Experience with architecture modeling and simulation tools, interconnect protocols, and system design workflows, including performance/power modeling environments, CXL, UALink, NVLink‑class fabrics, UCIe, Python, C++, SystemC, and architecture specification tools used to develop implementable designs for RTL, physical design, and packaging teams.

• Familiarity with photonic or optical compute concepts and their integration with electronic compute architectures will be considered a plus.

• Experience with heterogeneous compute architectures involving GPUs, DPUs, FPGAs, custom accelerators, or AI accelerator platforms will be considered a plus.

• Experience contributing to industry interconnect standards such as CXL Consortium, UALink, or UCIe Consortium will be considered a plus.

Benefits

Your Health and Future Matter. Your well‑being is paramount. We offer a comprehensive benefits package with outstanding insurance, pension and virtual stock options for your mental, physical, and financial health. Your peace of mind is our priority – in the present and future.

We encourage qualified individuals from any background to apply.