Senior Engineer Verification

Darum lohnt es sich

Your Role Key responsibilities in your new role To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs.

Leading a project for AMS requirements is a value add Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort – coming up with alternative verification plans- Full Self-motivated to drive new scope expansion proposals mapping to business value Mentoring junior engineers in creating problem solving mindset Establishing cross collaboration with other domains and coming up with proposals in enhancing product development working approaches Your Profile Qualifications and skills to help you succeed Bachelors with 4+ years of experience Mentoring: Technical mentoring for junior engineers.

Instigate thought-provoking culture Candidate should have working experience with AMS Verification on multiple SOC’s or sub-systems/IPs Should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus Candidate should be familiar with the conc