Das ist der Job
Develop and integrate at‑speed test methodologies using OPCG for intra‑ and inter‑clock domain testing.
Darum lohnt es sich
Overview
Morse Micro is a leading manufacturer of next‑generation Wi‑Fi technology, focused on building 802.11ah chips for the Internet of Things. Responsibilities Own end‑to‑end DFT for wireless SoCs, including architecture, implementation, verification, tape‑out sign‑off, silicon bring‑up, and production support.
Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints. Architect and implement SCAN solutions, including chains, sub‑chains, masking, compressors, decompressors, SDCs, and ensure post‑synthesis SCAN DRC cleanliness.
Implement low‑power DFT techniques such as power‑aware scan, clock staggering, and test‑point insertion to meet ATE/package limits. Own MBIST integration and diagnostics for all on‑chip memories, including JTAG‑based debug diagnostic flows. Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test‑mode/pin‑mux control.
Integrate DFT for third‑party hardened IPs (e.g., PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration. Generate and validate ATPG (stuck‑at, transition, path‑delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring‑up/debug. Drive silicon debug, yi
