Darum lohnt es sich
Responsibilities Compilation and release of new analog circuit libraries (1.5V and 1.8V) for the Cadence Virtuoso development environment Checking cells for completeness of content and documentation Communication with external circuit developers and internally with other departments Submission of test chips on X-FAB multi-project wafer runs with following packaging for measurements Specification of analog IP cells for 0.18um and 0.11um technologies (e.g.
PLL, DCDC converters and auxilliary cells) Schematic design and layout of analog CMOS circuit cells with Cadence Virtuoso Simulation and verification of cell designs across process variations (corner simulation, Monte Carlo, DRC, LVS, parasitics extraction) Planning and design of complete test chips including IO-ring and bond diagrams Verification of entire test chips with DRC, LVS, ESD check Sign-off simulation of test chips after extraction of parasitic circuit elements Direct customer communication for analog inquiries (analysis of issues and consulting for design changes) Consulting of customers for new projects regarding process and module selection Dedicated technical contact person for one selected customer Support for the sales department during customer visits (road shows, trade fairs) Mentoring of younger colleagues and students (bachelor's and master's the
